1. Field of the Invention
The present invention relates to circuits, and, in particular, to a phase-locked loop incorporating multiple oscillators.
2. Description of the Related Art
A phase locked loop (PLL) is widely used in communications systems for clock synthesis and generation. The PLL is a closed-loop frequency-control system based on the phase difference between the input clock signal and the feedback output signal of a controlled oscillator. The main blocks of the PLL are the phase frequency detector (PFD), a charge pump, a loop filter, a voltage controlled oscillator (VCO), and counters. The VCO frequency range of oscillation directly determines the top and bottom oscillation rates of the PLL. A common application of a PLL is in a serializer-deserializer (SERDES) device. The range of standard specified clock rates a SERDES device can support, and its quality, is fundamental to the performance of the overall system employing the SERDES device. The top oscillation frequency. Rj and Pj levels (random and periodic jitter levels, respectively), tuning range (range of oscillation frequencies), and start-up margin are key performance measures for an PLL. These key performance measures are related and coupled to one another, making a design have direct performance measure trade-offs with each other in a conventional PLL design.
A high-performance PLL with a wide tuning range is difficult to implement for 10 GHz+ applications. The difficulty with implementing a wide-tuning range PLL is especially true for deep submicron standard CMOS technology with high gate and channel leakage, such as 40 nm geometry CMOS technology integrated circuit (IC) chips. The degradation in performance increases if the PLL operates in large system-on-chip (SoC environment, which is typical for SERDES applications. Furthermore, for production designs in the field, satisfactory performance over varying process, voltage, and temperature (PVT) operation is required.
A single wide range LCVCO-based PLL, such as shown in FIG. 1A, offers better noise immunity to mid to high frequency supply noises than the multi-phase ring PLL architecture, and is particularly suitable for SoC applications. A lower frequency reference clock (Refclk) and a scaled version of the PLL output is applied to PFD 101, which generates an error signal proportional to the difference between its input signals. Based on this error signal, charge pump 102 increases or decreases charge applied to loop filter 103. Charge from charge pump 102 appears as a voltage Vtune provided by loop filter 103 that controls the oscillation frequency of LCVCO 104. LCVCO 104 is a wide range, full rate LCVCO which provides a signal to the channel at a desired oscillation frequency. In addition, this output signal from LCVCO 104 is provided to counter 105, which scales down the output frequency by NI, which scaled signal is then provided to PFD 101.
For the single wide range LCVCO-based PLL of FIG. 1A, a complimentary cross-coupled VCO architecture might be employed for LCVCO 104, such as shown in FIG. 1B. LCVCO comprises a cross-coupled differential amplifier 151 with an LC tank in its feedback path. This LC tank is composed of inductance provided by inductor 202 (with exemplary inductive value L1) and a capacitance provided by parallel-coupled varactors 154 (with exemplary capacitive values Var1) and switched capacitor banks 153 (with exemplary capacitive values C1). Switched capacitor banks 153 are optionally included to extend the tuning range of the VCO. The VCO oscillates as given in equation (1):
                              ω          osc                =                              {                          L              ·                              (                                                      C                    tran                                    +                                      C                    load                                    +                                      C                    rtg                                    +                                      C                    swcap                                    +                                      C                    var                                                  )                                      }                                              -              t                        2                                              (        1        )            where L is the inductance, Ctran and Cload are the loadings from the negative gm transistors of the differential amplifier and the following stage circuitry, Crig is the circuit's routing and parasitic capacitance for the implementation, Csweap is the switched-capacitor bank capacitance, and Cvar is the varactor capacitance. The VCO gain is given by equation (2):
                              k          vco                =                              -                          L              2                                ⁢                      ω            osc            2                    ⁢                                    ∂                              C                var                                                    ∂                              V                tune                                                                        (        2        )            
As shown, coupling and trade-offs exist between the top oscillation frequency, the tuning range, the start-up margin, and the jitter performance. Switched-capacitor banks might be employed to extend the tuning range of the VCO, but the switched capacitor banks' Q factor limits the jitter performance of the overall circuit. Increasing the Q value increases the VCO's off-capacitance and reduces the top oscillation frequency. Further rate reduction comes from the Crig growth for the extra routing needed for, and parasitic coupling from, the large switched capacitor banks; and from the Ctran growth for sufficient start-up margin to cover the loading from the switched capacitor banks. Extending the tuning range by raising the varactor size, on the other hand, increases kvco and the jitter sensitivity. Therefore, obtaining both top oscillation at a relatively high frequency and bottom oscillation at a relatively low frequency, and while having sufficient start-up margin and good jitter performance, from a single LCPLL is difficult to achieve.
Consequently, designers have attempted to increase the tuning range of a PLL by simply adding separate LCVCO circuits, sometimes termed direct expansion. In such designs, unused ones of the separate LCVCO circuits are turned off or otherwise disabled. However, each unused LCVCO circuit might present a capacitive and resistive loading to the loop filter of the PLL. When a single LCVCO PLL is extended to have two LCVCO PLLs (a dual LCVCO PLL) and four LCVCO PLLs (a quad LCVCO PLL), the added impedance of the dormant circuit elements can have unwanted effects on operation. These variations in PVT performance from the dormant LCVCO impedance, especially at high oscillation frequency and small integrated circuit (IC) geometry, can cause the PLL to have unacceptable jitter performance and even exhibit unstable operation.